1. Field of the Invention
The present invention relates to a thin film transistor and a manufacturing method for the same, and more particularly, to reduction of a hydrogen passivation process time in a top gate type thin film transistor and a manufacturing method for the same.
2. Description of the Related Art
A polysilicon thin film transistor has equal to or more than 100 times of electron mobility of an amorphous silicon thin film transistor, and an N channel and P channel transistors can be formed as the polysilicon thin film transistors. For this reason, the polysilicon thin film transistor which is formed on a glass substrate can be applied to circuit elements such as a switching transistor of a high resolution liquid crystal display, a drive circuit and liquid crystal switching transistor of a driver integrated liquid crystal display, and a drive circuit transistor of various flat panel displays.
FIGS. 1A-1 to 1F-1 are diagrams illustrating cross sectional views of a polysilicon thin film transistor in a first conventional example of a manufacturing method. FIGS. 1A-2 to 1F-2 are diagrams illustrating plan views of the polysilicon thin film transistor in the manufacturing process.
As shown in FIGS. 1A-1 to 1A-2, a polysilicon thin film is formed on a glass substrate 1. Excimer laser light 3 is irradiated to the thin film such that the silicon thin film can absorb the excimer laser light 3 sufficiently. As a result, the amorphous silicon or polysilicon are fused and re-crystallized. In this way, high quality polysilicon film 2 is formed.
Next, as shown by FIGS. 1B-1 and 1B-2, the polysilicon film 2 is patterned in such an island manner. Then, a gate insulating film 4 such as a silicon oxide film is formed on the patterned polysilicon film 2 as a gate insulating film.
Next, as shown by FIGS. 1C-1 and 1C-2, a low resistance polysilicon gate electrode 5 in which impurity ions such as phosphorus ions are added in a high concentration, and a gate metal/alloy electrode 6 are deposited in this order and patterned to form a gate structure. The gate metal/alloy electrode 6 is formed of metals such as aluminum or metal silicide such as tungsten silicide.
Next, as shown by FIGS. 1D-1 and 1D-2, the ion implantation of the impurity ions 7 is performed to form source and drain areas 8, using a resist layer 15, the gate metal/alloy electrode 6 and the low resistance polysilicon gate electrode 5 as a mask. Then, the activation heat treatment is performed such that the impurity ions are arranged on the crystal lattice positions.
Next, as shown by FIG. 1E-1 and 1E-2, the substrate 1 is exposed to a hydrogen plasma atmosphere or a hydrogen atmosphere for 1 to 2 hours at the temperature of 200 to 400.degree. C. As a result, hydrogen atoms, hydrogen radicals or hydrogen ions are diffused into the thin film transistor (device). Thus, the hydrogen passivation process of the polysilicon film (hereinafter, to be also referred to as a hydrogenation process) is performed.
Last, as shown in FIGS. 1F-1 and 1F-2, an interlayer insulating film 10 is formed, contact halls 11 are opened and source and drain wiring electrodes 12 are formed.
In this way, the polysilicon thin film transistor is complete.
Recent years, the polysilicon film forming technique using the excimer laser annealing is established as described with reference to FIGS. 1A-1 to 1F-2. At that time, the process maximum temperature of the transistor is about 500 to 600 .degree. C. Therefore, non-expensive alkaline glass substrate can be used.
Also, various film forming techniques, etching techniques, photolithography techniques, impurity introduction techniques, the excimer laser annealing technique are developed in correspondence to use of a large size substrate. Because the thin film transistors can be formed on the non-expensive large glass substrate, the manufacturing cost falls. Thus, it is made possible to reduce the price of an application product so that the polysilicon thin film transistor application product market is created and extended.
In order to accelerate the market extension of the application products of the polysilicon thin film transistor, cost reduction is mainly important. For this purpose, the following matters are technically important in the thin film transistor manufacturing method:
(1) use of a large size glass; PA1 (2) manufacturing process at a lower temperature; and PA1 (3) increase of throughput. PA1 forming source and drain regions and an active region sandwiched by the source and drain regions on a substrate; PA1 forming a gate insulating film on the source and drain regions and the active region; PA1 forming a gate structure which includes a semiconductor gate and a gate electrode, wherein the semiconductor gate is formed on the gate insulating film above the active region, and the gate electrode is formed on the semiconductor gate such that the semiconductor gate has an exposure portion where the semiconductor gate is not covered by the gate electrode; and PA1 performing a hydrogen passivation after the gate structure is formed. PA1 depositing a semiconductor film on the gate insulating film; PA1 depositing a film for the gate electrode on the semiconductor film; PA1 patterning the semiconductor film and the film for the gate electrode at a time to form the semiconductor gate; and PA1 patterning the patterned film for the gate electrode to form the gate electrode with the exposure portion. PA1 depositing a semiconductor film on the gate insulating film; PA1 patterning the semiconductor film to form the semiconductor gate; PA1 depositing a film for the gate electrode on the semiconductor gate and the gate insulating film; PA1 patterning the film for the gate electrode to form the gate electrode with the exposure portion on the semiconductor gate. PA1 forming source and drain regions and an active region sandwiched by the source and drain regions on a substrate; PA1 forming a gate insulating film on the source and drain regions and the active region; PA1 forming a gate structure which includes a semiconductor gate and a gate electrode, wherein the semiconductor gate is formed on the gate insulating film above the active region, and the gate electrode is formed on the semiconductor gate such that the semiconductor gate has an exposure portion where the semiconductor gate is not covered by the gate electrode; and PA1 injecting at least one of hydrogen molecules, hydrogen ions and hydrogen radicals through the exposure portion of the semiconductor gate.
When attention is paid to the above problem (3) of them, a hydrogenation process is a cause for the reduction of the throughput among all the polysilicon thin film transistor manufacturing processes. The hydrogenation process is performed to hydrogen-terminate silicon dangling bonds existing in crystal grain boundary of the polysilicon acting as an active layer and an interface between the polysilicon film and the gate insulating film.
The hydrogenation process is generally performed in the last stage of the thin film transistor manufacturing method. The hydrogenation process time is about 1 to 2 hours and very long. This is because a normal transistor structure is the top gate type as shown in FIG. 2 or FIG. 3. In this type thin film transistor, hydrogen molecules, hydrogen ions or hydrogen radicals can hardly pass the gate wiring electrode 6, which is formed of metal and metal silicide. Therefore, most of the hydrogen molecules, hydrogen ions or hydrogen radicals move along the long distance diffusion course 14 and reach the polysilicon active region 13 to which the passivation should be performed as shown in second and third conventional examples of FIG. 2 and FIG. 3. In the third conventional example shown in FIG. 3, because a contact hall is smaller than a gate metal/alloy electrode 6 in area, the hydrogen molecules, hydrogen ions or hydrogen radicals diffuses from the top of active region 13, too. Therefore, the hydrogenation process efficiency is improved, compared with the second conventional example shown in FIG. 2.
However, the hydrogen molecules, hydrogen ions or hydrogen radicals must diffuse for the film thickness of an interlayer insulating film 10 and the distance for the contact hall. Thus, the substantial increase of the hydrogenation process efficiency can not be expected. FIG. 4 shows hydrogen concentration in the active region in a source and drain direction when the hydrogen molecules, hydrogen ions or hydrogen radicals are diffused through the diffusion routes shown in FIG. 2 or FIG. 3. As seen from FIG. 4, the hydrogenation process efficiency is very low in the active region central portion which is apart from the end of the gate electrode by 2 to 3 .mu.m. This causes the long hydrogenation process time.
In one of the methods of solving this problem, the hydrogenation process is performed before the gate wiring electrode is formed, so that the hydrogen molecules, hydrogen ions or hydrogen radicals can be diffused through the gate insulating film. In the usual thin film transistor method, impurity ion implantation into the source and drain regions is performed using the gate wiring electrode of metal or metal silicide as a mask, and then heat-treatment is performed at the temperature equal to or higher than 500.degree. C. for the impurity ion activation. For this reason, the hydrogen atoms bonded to silicon atoms are almost thermally dissociated during the heat treatment. Therefore, when the above method is applied, it is necessary that impurity ion activation equal to or lower than 350.degree. C. is established. In the present situation, this is difficult.
Therefore, the hydrogenation process Is strongly needed which is performed sufficiently in a short time after the impurity ion implantation using the gate electrode as the mask and the activation a re performed. Such a hydrogenation process is described in Japanese Laid Open Patent Application (JP-A-Heisei 7-38118).
In t his fourth conventional example, two gate electrode s a re formed on a single polysilicon active region such that the two gate electrodes are in parallel to each other and connected to each other at one end. Then, impurity ion implantation is performed. In this method, two channel regions with a short channel length are formed and the hydrogenation process is performed to the transistor with the two channel regions. Thus, the hydrogenation process is efficiently performed. FIG. 5 shows the structure of the thin film transistor. However, there are various problems in this thin film transistor manufacturing method.
First, there is an opening on the gate insulating film, and only an interlayer insulating film, and a protection film exist on the opening. For this reason, the quantity of moisture diffusing from the atmosphere into the gate insulating film becomes very much, compared with the case where the gate insulating film is covered by the gate electrode. As a result, the problem occurs in the device operational reliability.
Second, the polysilicon activation region to which the hydrogenation process should be performed is covered by the gate electrode. Therefore, it is impossible to substantially increase the hydrogenation process efficiency, unless each channel length is made very short.
Third, a low resistance polysilicon region exists between two channels between the source and the drain. This resistance components decreases the ON current of the transistor.
Therefore, the technique described in the Japanese Laid Open Patent Application (JP-AHeisei 7-38118) is not practical from the above reasons.
In addition, a thin film transistor manufacturing method is described in Japanese Laid Open Patent Application (JP-A-Showa 63-119270). In this reference, a thin film transistor is formed to have a gate electrode of polysilicon and then an interlayer insulating film and a protection film are formed. Subsequently, hydrogen ions are irradiated. However, in this method, hydrogen diffusion route is long.
Also, a thin film transistor manufacturing method is described in Japanese Laid Open Patent Application (JP-A-Showa 64-53553). In this reference, a substrate on which a thin film transistor has been completed is heated and hydrogen gas pressure is increased. In such a condition, hydrogen atoms are diffused in the thin film transistor. In this method, the hydrogen diffusion route is also long.
Also, a thin film transistor manufacturing method is described in Japanese Laid Open Patent Application (JP-A-Heisei 5-55521). In this reference, an active region is formed a gate electrode through a gate insulating film. Therefore, the reference is different from the present invention in the structure.
Also, a thin film transistor manufacturing method is described in Japanese Laid Open Patent Application (JP-A-Heisei 6-77484). In this reference, a channel layer has a 2-layer structure, a hydrogen supplying source is provided. between two channel layers.
Also, a thin film transistor manufacturing method is described in Japanese Laid Open Patent Application (JP-A-Heisei 6-314697). In this reference, a gate insulating film includes water or hydrogen, and hydrogen ions are supplied to the channel layer by applying a voltage.
Also, a thin film transistor manufacturing method Is described in Japanese Laid Open Patent Application (JP-A-Heisei 7-249772). In this reference, an interlayer insulating film 4, a silicon nitride film 8, and an amorphous silicon film 9 are formed on a thin film transistor in this order. Then, a hydrogen passivation process is performed. Thus, in the reference, the hydrogen diffusion route is long.
Also, a thin film transistor manufacturing method is described in Japanese Laid Open Patent Applications (JP-A-Heisei 7-14849 and JP-A-Heisei 7-58337). In this reference, a hydrogen passivation process and a impurity introduction process are performed to a polysilicon layer 12 before a gate insulating film is formed. However, in this reference, processes after the hydrogen passivation must be performed below 450.degree. C.
Also, a thin film transistor manufacturing method is described in Japanese Laid Open Patent Application (JP-A-Heisei 8-97431). In this reference, a hydrogenation process is performed after a gate electrode is formed. The gate electrode 14 has the same area has that of the active region 12a. Therefore, the diffusion route in the reference is the same as that in the second conventional example.